A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flops
نویسندگان
چکیده
We propose a low-power redundant flip-flop to be operated with high reliability over 1GHz clock frequency based on the low-power ACFF and the highly-reliable BCDMR FF. Its power dissipation is almost equivalent to transmission gate FFs at 10% data activity while paying 3x area penalty. Experiments by α-particle and neutron irradiation reveals its highly-reliable operations with no errors at 1.2V and 1GHz.
منابع مشابه
Radiation-Hardened Flip-Flops with Low Delay Overheads Using PMOS Pass-Transistors to Suppress a SET Pulse in a 65 nm FDSOI Process
We propose radiation-hardened flip-flops (FFs) based on the adaptive coupling FF (ACFF) with low dynamic power and short delay overheads in a 65 nm Fully Depleted Silicon On Insulator (FDSOI) process. We designed four FFs composed of the master latch with PMOS pass-transistors to reduce delay time overheads and the slave latch with stacked transistors for high soft-error tolerance. We evaluated...
متن کاملA new low power high reliability flip-flop robust against process variations
Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In ...
متن کاملIJSRD - International Journal for Scientific Research & Development| Vol. 3, Issue 09, 2015 | ISSN (online): 2321-0613
The timing elements and clock interconnection Networks such as flip-flops and latches, is One of the most power consuming components in modern very large Scale integration (VLSI) system. The area, power and transistor count will compared and designed using several latches and flip flop stages. Flip Flop is a circuit which is used to store state information. Power consumption is one of the main ...
متن کاملHigh-performance and Low-power Clock Branch Sharing Pseudo-NMOS Level Converting Flip-flop
Multi-Supply voltage design using Cluster Voltage Scaling (CVS) is an effective way to reduce power consumption without performance degradation. One of the major issues in this method is performance and power overheads due to insertion of Level Converting Flip-Flops (LCFF) at the interface from low-supply to high-supply clusters to simultaneously perform latching and level conversion. In this p...
متن کاملAnalysis of the Distance Dependent Multiple Cell Upset Rates on 65-nm Redundant Latches by a PHITS-TCAD Simulation System
Recently, the soft error rates of integrated circuits is increased by process scaling. Soft error decreases the tolerance of VLSIs. Charge sharing and bipolar effect become dominant when a particle hit on latches and flip-flop. soft error makes circuit more sensitive to Multiple Cell Upset (MCU). We analyze the MCU tolerance of redundant latches in 65 nm process by device simulation and particl...
متن کامل